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R5F72115D160FPV Datasheet(PDF) 633 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 633 Page - Renesas Technology Corp |
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633 / 1228 page ![]() Section 12 Port Output Enable 2 (POE2) Rev. 2.00 May. 08, 2008 Page 609 of 1200 REJ09B0344-0200 Figure 12.1 shows a block diagram of the POE2. TIOC3B TIOC4A TIOC4C TIOC4B TIOC4D POE3 POE1 POE0 POE7 POE4 POE8 TIOC3D TIOC3BS TIOC4AS TIOC4CS TIOC4BS TIOC4DS TIOC3DS SPOER Output level comparison circuit Input level detection circuit Falling edge detection circuit Low level sampling circuit Input level detection circuit Falling edge detection circuit Low level sampling circuit Input level detection circuit Falling edge detection circuit Low level sampling circuit P φ/8 P φ P φ/16 P φ/128 High-impedance request signal for MTU2 high-current pins High-impedance request signal for MTU2 channel 0 pins High-impedance request signal for MTU2S high-current pins Interrupt request signal Frequency divider POECR1, POECR2 Output level comparison circuit Output level comparison circuit Output level comparison circuit Output level comparison circuit Output level comparison circuit ICSR1: ICSR2: ICSR3: OCSR1: OCSR2: [Legend] Input level control/status register 1 Input level control/status register 2 Input level control/status register 3 Output level control/status register 1 Output level control/status register 2 SPOER: POECR1: POECR2: Software port output enable register Port output enable control register 1 Port output enable control register 2 Figure 12.1 Block Diagram of POE2 |
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