R5F72115D160FPV datasheet(737/1228 Pages) RENESAS

737 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 713 of 1200

REJ09B0344-0200

Figure 15.10 shows a sample flowchart for initializing the SCIF.

Start of initialization

Clear TE and RE bits

in SCSCR to 0

Set TFRST and RFRST bits

in SCFCR to 1 to clear

the FIFO buffer

After reading ER, DR,

and BRK flags in SCFSR,

write 0 to clear them

Set CKE[1:0] in SCSCR

(leaving TIE, RIE, TE,

and RE bits cleared to 0)

Set data transfer format

in SCSMR

Set RTRG[1:0] and TTRG[1:0] in SCFCR,

and clear TFRST and RFRST

Set value in SCBRR

Set TE and RE bits in SCSCR

to 1, and set TIE, RIE,

and REIE bits

End of initialization

Leave the TE and RE bits cleared

to 0 until the initialization almost

ends. Be sure to clear the TIE,

RIE, TE, and RE bits to 0.

Set the data transfer format in

SCSMR.

Set CKE[1:0].

Write a value corresponding to

the bit rate into SCBRR. This

is not necessary if an external

clock is used.

Set the TE or RE bit in SCSCR

to 1. Also set the TIE, RIE, and

REIE bits to enable the TXD,

RXD, and SCK pins to be used.

When transmitting, the TXD pin

will go to the mark state.

When receiving in clocked

synchronous mode with the

synchronization clock output (clock

master) selected, a clock starts to

be output from the SCK pin at this

point.

[1]

[2]

[3]

[4]

[5]

[2]

[3]

[4]

[5]

Figure 15.10 Sample Flowchart for SCIF Initialization

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