R5F72115D160FPV datasheet(736/1228 Pages) RENESAS

736 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 712 of 1200

REJ09B0344-0200

In clocked synchronous serial communication, each data bit is output on the communication line

from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of

the serial clock.

In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB

(last). After output of the MSB, the communication line remains in the state of the MSB.

In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the

serial clock.

(1)

Transmit/Receive Formats

The data length is fixed at eight bits. No parity bit can be added.

(2)

Clock

An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in

SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as

the SCIF transmit/receive clock.

When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight

clock pulses are output per transmitted or received character. When the SCIF is not transmitting or

receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs

while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive

FIFO data trigger number.

(3)

Transmitting and Receiving Data

• SCIF Initialization (Clocked Synchronous Mode)

Before transmitting, receiving, or changing the mode or communication format, the software must

clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF.

Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does

not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which

retain their previous contents.

R5F72115D160FPV Datasheet(PDF) 736 Page - Renesas Technology Corp