R5F72115D160FPV datasheet(740/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 716 of 1200

REJ09B0344-0200

• Receiving Serial Data (Clocked Synchronous Mode)

Figures 15.13 and 15.14 show sample flowcharts for receiving serial data. When switching from

asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that

ORER, PER, and FER are cleared to 0.

Start of reception

Read ORER flag in SCLSR

ORER = 1?

Read RDF flag in SCFSR

RDF = 1?

Read receive data in

SCFRDR, and clear RDF

flag in SCFSR to 0

All data received?

Clear RE bit in SCSCR to 0

End of reception

Yes

Error handling

[1] Receive error handling:

Read the ORER flag in SCLSR to identify

any error, perform the appropriate error

handling, then clear the ORER flag to 0.

Reception cannot be resumed while the

ORER flag is set to 1.

[2] SCIF status check and receive data read:

Read SCFSR and check that RDF = 1,

then read the receive data in SCFRDR,

and clear the RDF flag to 0. The transition

of the RDF flag from 0 to 1 can also be

identified by an RXI interrupt.

[3] Serial reception continuation procedure:

To continue serial reception, read at least

the receive trigger set number of receive

data bytes from SCFRDR, read 1 from the

RDF flag, then clear the RDF flag to 0.

The number of receive data bytes in

SCFRDR can be ascertained by reading

SCFRDR. However, the RDF bit is

cleared to 0 automatically when an RXI

interrupt activates the DMAC to read the

data in SCFRDR.

[1]

[2]

[3]

Figure 15.13 Sample Flowchart for Receiving Serial Data (1)

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