R5F72115D160FPV datasheet(744/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 720 of 1200

REJ09B0344-0200

15.5

SCIF Interrupts

The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),

receive FIFO data full (RXI), and break (BRI).

Table 15.12 shows the interrupt sources and their order of priority. The interrupt sources are

enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt

request is sent to the interrupt controller for each of these interrupt sources.

When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register

(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data

transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the

CPU.

When an RXI request is enabled by the RIE bit and the RDFE flag or the DR flag in SCFSR is set

to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer

performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU.

The RXI interrupt request caused by the DR flag is generated only in asynchronous mode.

When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt

without requesting an RXI interrupt.

The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that

there is receive data in SCFRDR.

Table 15.12 SCIF Interrupt Sources

Interrupt

Source

Description

DMAC

Activation

Priority on

Reset Release

BRI

Interrupt initiated by break (BRK) or overrun error

(ORER)

Not possible

High

ERI

Interrupt initiated by receive error (ER)

Not possible

RXI

Interrupt initiated by receive FIFO data full (RDF) or

data ready (DR)

Possible

TXI

Interrupt initiated by transmit FIFO data empty

(TDFE)

Possible

Low

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