R5F72115D160FPV datasheet(746/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 722 of 1200

REJ09B0344-0200

15.6.3

Restriction on DMAC Usage

When the DMAC writes data to SCFTDR due to a TXI interrupt request, the state of the TEND

flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in

such a case.

15.6.4

Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is

detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set

and the parity error flag (PER) may also be set.

Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF

receiver continues to operate.

15.6.5

Sending a Break Signal

The I/O condition and level of the TXD pin are determined by the SPB2IO and SPB2DT bits in

the serial port register (SCSPTR). This feature can be used to send a break signal.

Until TE bit is set to 1 (enabling transmission) after initializing, the TXD pin does not work.

During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and

SPB2DT bits should be set to 1 (high level output).

To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low

level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the

transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD

pin.

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