R5F72115D160FPV datasheet(747/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

747 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 723 of 1200

REJ09B0344-0200

15.6.6

Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the

SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.

Receive data is latched at the rising edge of the eighth base clock pulse.* The timing is shown in

figure 15.17.

10 11 12 13 14 15

16 clocks

8 clocks

Base clock

Receive data

(RxD)

Start bit

–7.5 clocks

+7.5 clocks

Synchronization

sampling timing

Data sampling

timing

Figure 15.17 Receive Data Sampling Timing in Asynchronous Mode

Note: * This is an example when ABCS = 0 in SCSEMR. When ABCS = 1, a frequency of 8 times

the bit rate becomes the basic clock, and receive data is sampled at the fourth rising edge

of the basic clock.

R5F72115D160FPV Datasheet(PDF) 747 Page - Renesas Technology Corp