R5F72115D160FPV datasheet(748/1228 Pages) RENESAS

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Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 724 of 1200

REJ09B0344-0200

The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.

Equation 1:

M = (0.5

−

)

− (L − 0.5) F −

(1 + F)

× 100 %

− 0.5

Where: M: Receive margin (%)

N: Ratio of clock frequency to bit rate

(N = 16 when ABCS = 0, and N = 8 when ABCS = 1)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute deviation of clock frequency

From equation 1, if F = 0, D = 0.5, and N = 16, the receive margin is 46.875%, as given by

equation 2.

Equation 2:

When D = 0.5 and F = 0:

M = (0.5

− 1/(2 × 16)) × 100%

= 46.875%

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

15.6.7

FER and PER Flags in the Serial Status Register (SCFSR)

The FER (framing error) and PER (parity error) flags in the serial status register (SCFSR) are

status flags of the receive FIFO data register (SCFRDR) to be read next. If the CPU or DMAC

reads the receive FIFO data register, the FER (framing error) and PER (parity error) flags of the

current receive data will be lost. To check the framing error and parity error status of the current

receive data correctly, the serial status register (SCFSR) should be read before the receive FIFO

data register is read.

R5F72115D160FPV Datasheet(PDF) 748 Page - Renesas Technology Corp