R5F72115D160FPV datasheet(753/1228 Pages) RENESAS

753 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 729 of 1200

REJ09B0344-0200

16.3.1

2C Bus Control Register 1 (ICCR1)

ICCR1 is an 8-bit readable/writable register that enables or disables the I

2C bus interface 3,

controls transmission or reception, and selects master or slave mode, transmission or reception,

and transfer clock frequency in master mode.

ICCR1 is initialized to H'00 by a power-on reset.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

ICE

RCVD

MST

TRS

CKS[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

ICE

R/W

2C Bus Interface 3 Enable

0: This module is halted. (SCL and SDA pins function

as ports.)

1: This bit is enabled for transfer operations. (SCL and

SDA pins are bus drive state.)

RCVD

R/W

Reception Disable

Enables or disables continuous reception when TRS =

0 and ICDRR is not read. If ICDRR cannot be read by

the rising of 8th clock cycle of SCL in master receive

mode, reception in byte units should be performed by

setting the RCVD bit to 1.

0: Enables continuous reception

1: Disables continuous reception

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