R5F72115D160FPV datasheet(758/1228 Pages) RENESAS

758 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 734 of 1200

REJ09B0344-0200

16.3.3

2C Bus Mode Register (ICMR)

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred

first, performs master mode wait control, and selects the transfer bit count.

ICMR is initialized to H'38 by a power-on reset. Bits BC[2:0] are initialized to H'0 by the IICRST

bit in ICCR2.

7654321

00111000

R/W

Bit:

Initial value:

R/W:

MLS

BCWP

BC[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

MLS

R/W

MSB-First/LSB-First Select

0: MSB-first

1: LSB-first

Set this bit to 0 when the I

2C bus format is used.

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

5, 4

⎯

All 1

Reserved

These bits are always read as 1. The write value should

always be 1.

BCWP

R/W

BC Write Protect

Controls the BC[2:0] modifications. When modifying the

BC[2:0] bits, this bit should be cleared to 0. In clocked

synchronous serial mode, the BC[2:0] bits should not

be modified.

0: When writing, values of the BC[2:0] bits are set.

1: When reading, 1 is always read.

When writing, settings of the BC[2:0] bits are invalid.

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