R5F72115D160FPV datasheet(762/1228 Pages) RENESAS

762 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 738 of 1200

REJ09B0344-0200

16.3.5

2C Bus Status Register (ICSR)

ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.

ICSR is initialized to H'00 by a power-on reset.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

TDRE

TEND

RDRF NACKF STOP AL/OVE

AAS

ADZ

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/W

Transmit Data Register Empty

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When data is written to ICDRT

[Setting conditions]

• When data is transferred from ICDRT to ICDRS and

ICDRT becomes empty

• When TRS is set

• When the start condition (including retransmission)

is issued

• When slave mode is changed from receive mode to

transmit mode

TEND

R/W

Transmit End

[Clearing conditions]

• When 0 is written in TEND after reading TEND = 1

• When data is written to ICDRT

[Setting conditions]

• When the ninth clock of SCL rises with the I2C bus

format while the TDRE flag is 1

• When the final bit of transmit frame is sent with the

clocked synchronous serial format

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