R5F72115D160FPV datasheet(765/1228 Pages) RENESAS

765 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 741 of 1200

REJ09B0344-0200

16.3.6

Slave Address Register (SAR)

SAR is an 8-bit readable/writable register that selects the communications format and sets the

slave address. In slave mode with the I

2C bus format, if the upper seven bits of SAR match the

upper seven bits of the first frame received after a start condition, this module operates as the slave

device.

SAR is initialized to H'00 by a power-on reset.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

SVA[6:0]

Bit

Bit Name

Initial

Value

R/W

Description

7 to 1

SVA[6:0]

0000000

R/W

Slave Address

These bits set a unique address in these bits,

differing form the addresses of other slave devices

connected to the I

2C bus.

R/W

Format Select

0: I

2C bus format is selected

1: Clocked synchronous serial format is selected

16.3.7

2C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the

space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to

ICDRS and starts transferring data. If the next transfer data is written to ICDRT during

transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.

7654321

11111111

R/W

Bit:

Initial value:

R/W:

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