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R5F72115D160FPV Datasheet(PDF) 767 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 767 Page - Renesas Technology Corp |
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767 / 1228 page  Section 16 I 2C Bus Interface 3 (IIC3) Rev. 2.00 May. 08, 2008 Page 743 of 1200 REJ09B0344-0200 16.3.10 NF2CYC Register (NF2CYC) NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the SCL and SDA pins. For details of the noise filter, see section 16.4.7, Noise Filter. NF2CYC is initialized to H'00 by a power-on reset. 7654321 0 00000000 RRRRRRR R/W Bit: Initial value: R/W: - - ----- NF2 CYC Bit Bit Name Initial Value R/W Description 7 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 NF2CYC 0 R/W Noise Filtering Range Select 0: The noise less than one cycle of the peripheral clock can be filtered out 1: The noise less than two cycles of the peripheral clock can be filtered out |
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