R5F72115D160FPV datasheet(763/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

763 / 1228 page

Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 739 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

RDRF

R/W

Receive Data Full

[Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When ICDRR is read

[Setting condition]

• When a receive data is transferred from ICDRS to

ICDRR

NACKF

R/W

No Acknowledge Detection Flag

[Clearing condition]

• When 0 is written in NACKF after reading NACKF

= 1

[Setting condition]

• When no acknowledge is detected from the receive

device in transmission while the ACKE bit in ICIER

is 1

STOP

R/W

Stop Condition Detection Flag

[Clearing condition]

• When 0 is written in STOP after reading STOP = 1

[Setting conditions]

• In master mode, when a stop condition is detected

after frame transfer

• In slave mode, when the slave address in the first

byte after the general call and detecting start

condition matches the address set in SAR, and then

the stop condition is detected

R5F72115D160FPV Datasheet(PDF) 763 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 763 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL