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R5F72115D160FPV Datasheet(PDF) 764 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 764 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface 3 (IIC3)
Rev. 2.00 May. 08, 2008 Page 740 of 1200
REJ09B0344-0200
Bit
Bit Name
Initial
Value
R/W
Description
2
AL/OVE
0
R/W
Arbitration Lost Flag/Overrun Error Flag
Indicates that arbitration was lost in master mode with
the I
2C bus format and that the final bit has been
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I
2C bus interface 3
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been occupied by another
master.
[Clearing condition]
• When 0 is written in AL/OVE after reading AL/OVE
= 1
[Setting conditions]
• If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
• When the SDA pin outputs high in master mode
while a start condition is detected
• When the final bit is received with the clocked
synchronous format while RDRF = 1
1
AAS
0
R/W
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA[6:0]
in SAR.
[Clearing condition]
• When 0 is written in AAS after reading AAS = 1
[Setting conditions]
• When the slave address is detected in slave receive
mode
• When the general call address is detected in slave
receive mode.
0
ADZ
0
R/W
General Call Address Recognition Flag
This bit is valid in slave receive mode with the I
2C bus
format.
[Clearing condition]
• When 0 is written in ADZ after reading ADZ = 1
[Setting condition]
• When the general call address is detected in slave
receive mode



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