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R5F72115D160FPV Datasheet(PDF) 780 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 780 Page - Renesas Technology Corp |
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780 / 1228 page  Section 16 I 2C Bus Interface 3 (IIC3) Rev. 2.00 May. 08, 2008 Page 756 of 1200 REJ09B0344-0200 Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 16.16 for the operation timing. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be output. 3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. This causes the SCL to be fixed to the high level after outputting one byte of the receive clock. 12 7 8 1 7 8 1 2 SCL MST TRS RDRF ICDRS ICDRR SDA (Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 16.15 Receive Mode Operation Timing |
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