R5F72115D160FPV datasheet(782/1228 Pages) RENESAS

Part #	R5F72115D160FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family

PDF	1228 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 16 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 May. 08, 2008 Page 758 of 1200

REJ09B0344-0200

16.4.7

Noise Filter

The logic levels at the SCL and SDA pins are routed through noise filters before being latched

internally. Figure 16.17 shows a block diagram of the noise filter circuit.

The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input

signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed

forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this

signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do

not agree, the previous value is held.

NF2CYC

SCL or SDA

input signal

Internal

SCL or SDA

signal

Sampling clock

Sampling

clock

Peripheral clock

cycle

Latch

Match

detector

Latch

Match

detector

Figure 16.17 Block Diagram of Noise Filter

R5F72115D160FPV Datasheet(PDF) 782 Page - Renesas Technology Corp