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R5F72115D160FPV Datasheet(PDF) 835 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 835 Page - Renesas Technology Corp |
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835 / 1228 page  Section 19 Pin Function Controller (PFC) Rev. 2.00 May. 08, 2008 Page 811 of 1200 REJ09B0344-0200 19.1.1 Port A I/O Registers H, L (PAIORH, PAIORL) PAIORH and PAIORL are 16-bit readable/writable registers that are used to set the pins on port A as inputs or outputs. Bits PA25IOR to PA0IOR correspond to pins PA25 to PA0. PAIORH and PAIORL are enabled when the port A pins are functioning as general-purpose inputs/outputs (PA25 to PA0) and for the TIOC input/output of the MTU2. In other states, they are disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORH or PAIORL is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 10 of PAIORH are reserved. These bits are always read as 0. The write value should always be 0. PAIORH and PAIORL are initialized to H'0000 by a power-on reset; but are not initialized by a manual reset or in sleep mode or software standby mode. (1) Port A I/O Register H (PAIORH) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: -- -- - - PA25 IOR PA24 IOR PA23 IOR PA22 IOR PA21 IOR PA20 IOR PA19 IOR PA18 IOR PA17 IOR PA16 IOR (2) Port A I/O Register L (PAIORL) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: PA13 IOR PA12 IOR PA11 IOR PA9 IOR PA8 IOR PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR PA15 IOR PA14 IOR PA10 IOR |
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