R5F72115D160FPV datasheet(987/1228 Pages) RENESAS

987 / 1228 page

Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 963 of 1200

REJ09B0344-0200

The received data are checked in the following ways.

1. Input frequency

The value of the received input frequency is checked to see if it is within the range of the

minimum and maximum values of input frequency for the selected clock mode of the selected

device. A value outside the range generates an input frequency error.

2. Multiplier

The value of the received multiplier is checked to see if it matches a multiplier or divisor that

is available for the selected clock mode of the selected device. A value that does not match an

available ratio generates a frequency multiplier error.

3. Operating frequency

The operating frequency is calculated from the received input frequency and the frequency

multiplier or divisor. The input frequency is the frequency of the clock signal supplied to the

LSI, while the operating frequency is the frequency at which the LSI is actually driven. The

following formulae are used for this calculation.

Operating frequency = input frequency

× multiplier, or

Operating frequency = input frequency / divisor

The calculated operating frequency is checked to see if it is within the range of the minimum

and maximum values of the operating frequency for the selected clock mode of the selected

device. A value outside the range generates an operating frequency error.

4. Bit rate

From the peripheral operating frequency (P

φ) and the bit rate (B), the value (= n) of the clock

select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate

checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate

selection error. The following formula is use to calculate the error.

Error (%) = [

] - 1

× 100

(N + 1)

× B × 64 × 22n-1

φ × 106

R5F72115D160FPV Datasheet(PDF) 987 Page - Renesas Technology Corp