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R5F72115D160FPV Datasheet(PDF) 1016 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 1016 Page - Renesas Technology Corp |
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1016 / 1228 page ![]() Section 23 Power-Down Modes Rev. 2.00 May. 08, 2008 Page 992 of 1200 REJ09B0344-0200 Table 23.1 States of Power-Down Modes State* Power-Down Mode Transition Conditions CPG CPU CPU Register On-Chip Memory On-Chip Peripheral Modules External Memory Canceling Procedure Sleep mode Execute SLEEP instruction with STBY bit cleared to 0 in STBCR Runs Halts Held Runs (RAM) Halts (Flash memory) Runs Auto- refreshing • Interrupt • Manual reset • Power-on reset • DMA address error Software standby mode Execute SLEEP instruction with STBY bit set to 1 in STBCR Halts Halts Held Halts (contents are held) Halts Self- refreshing • NMI interrupt • IRQ interrupt • Manual reset • Power-on reset Module standby function Set the MSTP bits in STBCR2, STBCR3, and STBCR4 to 1 Runs Runs Held Specified module halts (contents are held) Specified module halts Auto- refreshing • Clear MSTP bit to 0 • Power-on reset (only for H-UDI, UBC, and DMAC) Note: * The pin state is retained or set to high impedance. For details, see appendix A, Pin States. |
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