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R5F72115D160FPV Datasheet(PDF) 1019 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 1019 Page - Renesas Technology Corp |
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1019 / 1228 page  Section 23 Power-Down Modes Rev. 2.00 May. 08, 2008 Page 995 of 1200 REJ09B0344-0200 23.3.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is possible. 7654321 0 00000000 R/W R R R R R R R Bit: Initial value: R/W: STBY ------- Bit Bit Name Initial Value R/W Description 7 STBY 0 R/W Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode. 1: Executing SLEEP instruction puts chip into software standby mode. 6 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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