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R5F72115D160FPV Datasheet(PDF) 1017 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 1017 Page - Renesas Technology Corp |
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1017 / 1228 page  Section 23 Power-Down Modes Rev. 2.00 May. 08, 2008 Page 993 of 1200 REJ09B0344-0200 23.1.2 Reset A reset is used when the power is turned on or to run the LSI again from the initialized state. There are two types of reset: power-on reset and manual reset. In a power-on reset, all the ongoing processing is halted and any unprocessed events are canceled, and the reset processing starts immediately. On the other hand, a manual reset does not interrupt processing to retain external memory data. Conditions for generating a power-on reset or manual reset are as follows: (1) Power-on Reset 1. A low level is input to the RES pin. 2. The watchdog timer (WDT) starts counting with the WT/ IT bit in WTCSR set to 1 and with the RSTS bit in WRCSR set to 0 while the RSRE bit in WRCSR is 1, and the counter overflows. 3. The H-UDI reset is generated (for details on the H-UDI reset, see section 24, User Debugging Interface (H-UDI)). (2) Manual Reset 1. A low level is input to the MRES pin. 2. The WDT starts counting with the WT/ IT bit in WTCSR set to 1 and with the RSTS bit in WRCSR set to 1 while the RSRE bit in WRCSR is 1, and the counter overflows. |
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