R5F72115D160FPV datasheet(1020/1228 Pages) RENESAS

1020 / 1228 page

Section 23 Power-Down Modes

Rev. 2.00 May. 08, 2008 Page 996 of 1200

REJ09B0344-0200

23.3.2

Standby Control Register 2 (STBCR2)

STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-

down modes. STBCR2 is initialized to H'00 by a power-on reset but retains its previous value by a

manual reset or in software standby mode. Only byte access is possible.

7654321

00000000

R/W

Bit:

Initial value:

R/W:

MSTP

Bit

Bit Name

Initial

Value

R/W

Description

MSTP10

R/W

Module Stop 10

When the MSTP10 bit is set to 1, the supply of the

clock to the H-UDI is halted.

0: H-UDI runs.

1: Clock supply to H-UDI halted.

MSTP9

R/W

Module Stop 9

When the MSTP9 bit is set to 1, the supply of the

clock to the UBC is halted.

0: UBC runs.

1: Clock supply to UBC halted.

MSTP8

R/W

Module Stop 8

When the MSTP8 bit is set to 1, the supply of the

clock to the DMAC is halted.

0: DMAC runs.

1: Clock supply to DMAC halted.

4 to 0

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R5F72115D160FPV Datasheet(PDF) 1020 Page - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 1020 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL