R5F72115D160FPV datasheet(1031/1228 Pages) RENESAS

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Section 23 Power-Down Modes

Rev. 2.00 May. 08, 2008 Page 1007 of 1200

REJ09B0344-0200

(2)

Exit from Software Standby Mode

Software standby mode is exited by interrupts (NMI or IRQ) or a reset (manual reset or power-on

reset).

(a)

Exit from Software Standby by an Interrupt

When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE)

in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling edge or

rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and

IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected,

clock oscillation is started. This clock pulse is supplied only to the oscillation settling counter

(WDT) used to count the oscillation settling time.

After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer

control/status register (WTCSR) of the WDT before the transition to software standby mode, the

WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock

pulse will be supplied to the entire chip after this overflow. Software standby mode is cleared and

NMI interrupt exception handling (IRQ interrupt exception handling in the case of IRRQ) starts.

When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0]

bits so that the WDT overflow period will be equal to or longer than the oscillation settling time.

The clock output phase of the CK pin may be unstable immediately after detecting an interrupt

and until software standby mode is canceled. When software standby mode is canceled by the

falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby

mode (when the clock pulse stops) and should be low when the CPU returns from software

standby mode (when the clock is initiated after the oscillation settling). When software standby

mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU

enters software standby mode (when the clock pulse stops) and should be high when the CPU

returns from software standby mode (when the clock is initiated after the oscillation settling) (This

is the same with the IRQ pin.)

(b)

Exit from Software Standby by a Reset

When the

RES or MRES pin is driven low, this LSI enters the power-on reset or manual reset

state, and software standby mode is exited.

Keep the

RES or MRES pin low until the clock oscillation settles.

Internal clock pulses are output continuously on the CK pin.

R5F72115D160FPV Datasheet(PDF) 1031 Page - Renesas Technology Corp