R5F72115D160FPV datasheet(1029/1228 Pages) RENESAS

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Section 23 Power-Down Modes

Rev. 2.00 May. 08, 2008 Page 1005 of 1200

REJ09B0344-0200

23.4

Operation

23.4.1

Sleep Mode

(1)

Transition to Sleep Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the

program execution state to sleep mode. Although the CPU halts immediately after executing the

SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules

continue to run in sleep mode. Clock pulses are output continuously on the CK pin.

(2)

Canceling Sleep Mode

Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address

error, or reset (manual reset or power-on reset).

• Canceling with an interrupt

When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and

interrupt exception handling is executed. When the priority level of the generated interrupt is

equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,

or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt

request is not accepted and sleep mode is not canceled.

• Canceling with a DMA address error

When a DMA address error occurs, sleep mode is canceled and DMA address error exception

handling is executed.

• Canceling with a reset

Sleep mode is canceled by a power-on reset or a manual reset.

23.4.2

Software Standby Mode

(1)

Transition to Software Standby Mode

The LSI switches from a program execution state to software standby mode by executing the

SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the

CPU but also the clock and on-chip peripheral modules halt. The clock output from the CK pin

also halts.

The contents of the CPU remain unchanged. Some registers of on-chip peripheral modules are,

however, initialized. Table 23.4 shows the states of peripheral module registers in software

standby mode.

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