R5F72115D160FPV datasheet(1025/1228 Pages) RENESAS

1025 / 1228 page

Section 23 Power-Down Modes

Rev. 2.00 May. 08, 2008 Page 1001 of 1200

REJ09B0344-0200

23.3.5

System Control Register 1 (SYSCR1)

SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM.

SYSCR1 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset

or in software standby mode. Only byte access is possible.

When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME

bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an

undefined value is returned when reading data or fetching an instruction from the on-chip RAM,

and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1.

Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an

instruction to read from or write to the same arbitrary address in each page before setting the

RAME bit. If such an instruction is not executed, the data last written to each page may not be

written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be

located immediately after the instruction to write to SYSCR1. If an on-chip RAM access

instruction is set, normal access is not guaranteed.

To enable the on-chip RAM by setting the RAME bit to 1, place an instruction to read data from

SYSCR1 immediately after an instruction to write to SYSCR1. If an instruction to access the on-

chip RAM is placed immediately after the instruction to write to SYSCR1, normal access is not

guaranteed.

7654321

11111111

RRRR

R/W

Bit:

Initial value:

R/W:

RAME3 RAME2 RAME1 RAME0

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

⎯

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

RAME3

R/W

RAM Enable 3 (corresponding RAM addresses:

H'FFF86000 to H'FFF87FFF)

0: On-chip RAM disabled

1: On-chip RAM enabled

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