R5F72115D160FPV datasheet(1036/1228 Pages) RENESAS

1036 / 1228 page

Section 24 User Debugging Interface (H-UDI)

Rev. 2.00 May. 08, 2008 Page 1012 of 1200

REJ09B0344-0200

24.2

Input/Output Pins

Table 24.1

Pin Configuration

Pin Name

Symbol

I/O

Function

H-UDI serial data input/output

clock pin

TCK

Input

Data is serially supplied to the H-UDI from

the data input pin (TDI), and output from

the data output pin (TDO), in

synchronization with this clock.

Mode select input pin

TMS

Input

The state of the TAP control circuit is

determined by changing this signal in

synchronization with TCK. For the protocol,

see figure 24.2.

H-UDI reset input pin

TRST

Input

Input is accepted asynchronously with

respect to TCK, and when low, the H-UDI is

reset.

TRST must be low for a constant

period when power is turned on regardless

of using the H-UDI function. See section

24.4.2, Reset Configuration, for more

information.

H-UDI serial data input pin

TDI

Input

Data transfer to the H-UDI is executed by

changing this signal in synchronization with

TCK.

H-UDI serial data output pin

TDO

Output

Data read from the H-UDI is executed by

reading this pin in synchronization with

TCK. The initial value of the data output

timing is the TCK falling edge. This can be

changed to the TCK rising edge by

inputting the TDO change timing switch

command to SDIR. See section 24.4.3,

TDO Output Timing, for more information.

ASE mode select pin

ASEMD*

Input

If a low level is input at the

ASEMD pin

while the

RES pin is asserted, ASE mode is

entered; if a high level is input, normal

mode is entered. In ASE mode, dedicated

emulator function can be used. The input

level at the

ASEMD pin should be held for

at least one cycle after

RES negation.

Note:

When the emulator is not in use, fix this pin to the high level.

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