R5F72115D160FPV datasheet(1040/1228 Pages) RENESAS

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Section 24 User Debugging Interface (H-UDI)

Rev. 2.00 May. 08, 2008 Page 1016 of 1200

REJ09B0344-0200

24.4.2

Reset Configuration

Table 24.4

Reset Configuration

ASEMD*1

RES

TRST

Chip State

Power-on reset and H-UDI reset

Power-on reset

H-UDI reset only

Normal operation

Reset hold*

Power-on reset

H-UDI reset only

Normal operation

Notes: 1. Performs normal mode and ASE mode settings

ASEMD = H, normal mode

ASEMD = L, ASE mode

2. In ASE mode, reset hold is entered if the

TRST pin is driven low while the RES pin is

negated. In this state, the CPU does not start up. When

TRST is driven high, H-UDI

operation is enabled, but the CPU does not start up. The reset hold state is cancelled

by a power-on reset.

24.4.3

TDO Output Timing

The initial value of the TDO change timing is to perform data output from the TDO pin on the

TCK falling edge. However, setting a TDO change timing switch command in SDIR via the H-

UDI pin and passing the Update-IR state synchronizes the TDO change timing to the TCK rising

edge. Thereafter the TDO change timing cannot be changed unless a power-on reset that asserts

the

TRST pin simultaneously is performed.

TDO

(initial value)

TCK

TDO

(after execution of TDO change

timing switch command)

tTDOD

Figure 24.3 H-UDI Data Transfer Timing

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