R5F72115D160FPV datasheet(1041/1228 Pages) RENESAS

1041 / 1228 page

Section 24 User Debugging Interface (H-UDI)

Rev. 2.00 May. 08, 2008 Page 1017 of 1200

REJ09B0344-0200

24.4.4

H-UDI Reset

An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset

is of the same kind as a power-on reset. An H-UDI reset is released by setting an H-UDI reset

negate command. The required time between the H-UDI reset assert command and H-UDI reset

negate command is the same as time for keeping the

RES pin low to apply a power-on reset.

H-UDI reset assert

H-UDI reset negate

SDIR

Chip internal reset

CPU state

Fetch the initial values of PC and SR from

the exception handling vector table

Figure 24.4 H-UDI Reset

24.4.5

H-UDI Interrupt

The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in

SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the

exception service routine start address from the exception handling vector table, jumping to that

address, and starting program execution from that address. This interrupt request has a fixed

priority level of 15.

H-UDI interrupts are accepted in sleep mode, but not in software standby mode.

R5F72115D160FPV Datasheet(PDF) 1041 Page - Renesas Technology Corp