R5F72115D160FPV datasheet(1045/1228 Pages) RENESAS

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Section 26 List of Registers

Rev. 2.00 May. 08, 2008 Page 1021 of 1200

REJ09B0344-0200

Section 26 List of Registers

This section gives information on the on-chip I/O registers of this LSI in the following structures.

1. Register Addresses (by functional module, in order of the corresponding section numbers)

• Registers are described by functional module, in order of the corresponding section numbers.

• Access to reserved addresses which are not described in this register address list is prohibited.

• When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian

mode is selected.

2. Register Bits

• Bit configurations of the registers are described in the same order as the Register Addresses

(by functional module, in order of the corresponding section numbers).

• Reserved bits are indicated by — in the bit name.

• No entry in the bit-name column indicates that the whole register is allocated as a counter or

for holding data.

3. Register States in Each Operating Mode

• Register states are described in the same order as the Register Addresses (by functional

module, in order of the corresponding section numbers).

• For the initial state of each bit, refer to the description of the register in the corresponding

section.

• The register states described are for the basic operating modes. If there is a specific reset for an

on-chip peripheral module, refer to the section on that on-chip peripheral module.

4. Notes when Writing to the On-Chip Peripheral Modules

• To access an on-chip module register, two or more peripheral module clock (Pf) cycles are

required. Care must be taken in system design. When the CPU writes data to the internal

peripheral registers, the CPU performs the succeeding instructions without waiting for the

completion of writing to registers. For example, a case is described here in which the system is

transferring to the software standby mode for power savings. To make this transition, the

SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1.

However a dummy read of the STBCR register is required before executing the SLEEP

instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the

STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy

read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the

change by internal peripheral registers while performing the succeeding instructions, execute a

dummy read of registers to which write instruction is given and then perform the succeeding

instructions.

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