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H838532H Datasheet(PDF) 284 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 284 Page - Renesas Technology Corp |
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284 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 264 of 484 REJ09B0436-0100 Set I bit to 1 in CCR Manipulate port mode register TMIG confirmation time Clear interrupt request flag to 0 Clear I bit to 0 in CCR Disable interrupts. (Interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) After manipulating he port mode register, wait for the TMIG confirmation time (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0. Enable interrupts Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG. Figure 9.16 shows an example of the operation in this case. Counter cleared TCG H'FF H'00 Input capture input signal Input capture register GF Input capture register GR Figure 9.16 Timer G Application Example |
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