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H838532H Datasheet(PDF) 285 Page - Renesas Technology Corp |
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H838532H Datasheet(HTML) 285 Page - Renesas Technology Corp |
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285 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 265 of 484 REJ09B0436-0100 9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. (1) Features Features of the watchdog timer are given below. • Incremented by internal clock source (φ/8192 or φw/32). • A reset signal is generated when the counter overflows. The overflow period can be set from from 1 to 256 times 8192/ φ or 32/φw (from approximately 4 ms to 1000 ms when φ = 2.00 MHz). • Use of module standby mode enables this module to be placed in standby mode independently when not used. (2) Block Diagram Figure 9.17 shows a block diagram of the watchdog timer. PSS TCSRW TCW φ/8192 Notation: TCSRW: TCW: PSS: φ φw/32 Reset signal Timer control/status register W Timer counter W Prescaler S Figure 9.17 Block Diagram of Watchdog Timer |
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