H838532H datasheet(286/508 Pages) RENESAS

286 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 266 of 484

REJ09B0436-0100

(3) Register Configuration

Table 9.17 shows the register configuration of the watchdog timer.

Table 9.17

Watchdog Timer Registers

Name

Abbr.

R/W

Initial Value

Address

Timer control/status register W

TCSRW

R/W

H'AA

H'FFB2

Timer counter W

TCW

R/W

H'00

H'FFB3

Clock stop register 2

CKSTPR2

R/W

H'FF

H'FFFB

Port mode register 3

PMR3

R/W

H'04

H'FFCA

9.6.2

(1) Timer Control/Status Register W (TCSRW)

Bit

Initial value

Read/Write

B6WI

TCWE

R/(W)*

B4WI

TCSRWE

R/(W)*

B2WI

WRST

R/(W)*

WDON

R/(W)*

B0WI

Note: * Write is permitted only under certain conditions, which are given in the descriptions of

the individual bits.

TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,

controls watchdog timer operations, and indicates operating status.

Bit 7: Bit 6 write inhibit (B6WI)

Bit 7 controls the writing of data to bit 6 in TCSRW.

Bit 7

B6WI

Description

Bit 6 is write-enabled

Bit 6 is write-protected

(initial value)

This bit is always read as 1. Data written to this bit is not stored.

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