HD6432351 datasheet(706/1025 Pages) RENESAS

706 / 1025 page

Section 17 RAM

Rev. 3.00 Sep 15, 2006 page 672 of 988

REJ09B0330-0300

17.1.2

The on-chip RAM is controlled by SYSCR. Table 17.1 shows the address and initial value of

SYSCR.

Table 17.1 RAM Register

Name

Abbreviation

R/W

Initial Value

Address*

System control register

SYSCR

R/W

H'01

H'FF39

Note:

* Lower 16 bits of the address.

17.2

17.2.1

System Control Register (SYSCR)

—

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

Bit

Initial value

R/W

The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in

SYSCR, see section 3.2.2, System Control Register (SYSCR).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset state is released. It is not initialized in software standby mode.

Bit 0

RAME

Description

On-chip RAM is disabled

On-chip RAM is enabled

(Initial value)

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