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HD6432351 Datasheet(PDF) 707 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 707 Page - Renesas Technology Corp |
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707 / 1025 page ![]() Section 17 RAM Rev. 3.00 Sep 15, 2006 page 673 of 988 REJ09B0330-0300 17.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFF400 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 17.4 Usage Note DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0. |
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