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HD6432351 Datasheet(PDF) 711 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 711 Page - Renesas Technology Corp |
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711 / 1025 page  Section 19 Clock Pulse Generator Rev. 3.00 Sep 15, 2006 page 677 of 988 REJ09B0330-0300 Section 19 Clock Pulse Generator 19.1 Overview The H8S/2350 Group has a built-in clock pulse generator (CPG) that generates the system clock ( φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium- speed clock divider, and a bus master clock selection circuit. 19.1.1 Block Diagram Figure 19.1 shows a block diagram of the clock pulse generator. EXTAL XTAL Duty adjustment circuit Oscillator Medium- speed divider System clock to φ pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC φ/2 to φ/32 SCK2 to SCK0 SCKCR Bus master clock selection circuit Figure 19.1 Block Diagram of Clock Pulse Generator |
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