HD6432351 datasheet(712/1025 Pages) RENESAS

712 / 1025 page

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 15, 2006 page 678 of 988

REJ09B0330-0300

19.1.2

The clock pulse generator is controlled by SCKCR. Table 19.1 shows the register configuration.

Table 19.1 Clock Pulse Generator Register

Name

Abbreviation

R/W

Initial Value

Address*

System clock control register

SCKCR

R/W

H'00

H'FF3A

Note:

* Lower 16 bits of the address.

19.2

19.2.1

System Clock Control Register (SCKCR)

PSTOP

R/W

—

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs

φ clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φφφφ Clock Output Disable (PSTOP): Controls φ output.

Description

Bit 7

PSTOP

Normal Operation

Sleep Mode

Software

Standby Mode

Hardware

Standby Mode

φ output (initial value)

φ output

Fixed high

High impedance

Fixed high

High impedance

Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

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