HD6432351 datasheet(713/1025 Pages) RENESAS

713 / 1025 page

Section 19 Clock Pulse Generator

Rev. 3.00 Sep 15, 2006 page 679 of 988

REJ09B0330-0300

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus

master.

Bit 2

SCK2

Bit 1

SCK1

Bit 0

SCK0

Description

Bus master is in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

—

19.3

Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

19.3.1

Connecting a Crystal Resonator

Circuit Configuration

A crystal resonator can be connected as shown in the example in figure 19.2. Select the damping

resistance Rd according to table 19.2. An AT-cut parallel-resonance crystal should be used.

EXTAL

XTAL

CL2

CL1

CL1 = CL2 = 10 to 22pF

Figure 19.2 Connection of Crystal Resonator (Example)

Table 19.2 Damping Resistance Value

Frequency (MHz)

Rd (

Ω

Ω)

500

200

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