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HD6432351 Datasheet(PDF) 717 Page - Renesas Technology Corp

Part # HD6432351
Description  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datasheet(HTML) 717 Page - Renesas Technology Corp

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Section 19 Clock Pulse Generator
Rev. 3.00 Sep 15, 2006 page 683 of 988
REJ09B0330-0300
19.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (
φ).
19.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate
φ/2, φ/4, φ/8, φ/16, and φ/32.
19.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (
φ) or one of the medium-speed
clocks (
φ/2, φ/4, or φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.



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