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HD6432351 Datasheet(PDF) 720 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 720 Page - Renesas Technology Corp |
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720 / 1025 page  Section 20 Power-Down Modes Rev. 3.00 Sep 15, 2006 page 686 of 988 REJ09B0330-0300 Table 20.1 Operating Modes CPU Modules Operating Mode Transition Condition Clearing Condition Oscillator Registers Registers I/O Ports High speed mode Control register Functions High speed Functions High speed Functions High speed Medium- speed mode Control register Functions Medium speed Functions High/ medium speed* 1 Functions High speed Sleep mode Instruction Interrupt Functions Halted Retained High speed Functions High speed Module stop mode Control register Functions High/ medium speed Functions Halted Retained/ reset* 2 Retained Software standby mode Instruction External interrupt Halted Halted Retained Halted Retained/ reset* 2 Retained Hardware standby mode Pin Halted Halted Undefined Halted Reset High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their state. 20.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 20.2 summarizes these registers. Table 20.2 Power-Down Mode Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'08 H'FF38 System clock control register SCKCR R/W H'00 H'FF3A Module stop control register H MSTPCRH R/W H'3F H'FF3C Module stop control register L MSTPCRL R/W H'FF H'FF3D Note: * Lower 16 bits of the address. |
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