HD6432351 datasheet(723/1025 Pages) RENESAS

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Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 689 of 988

REJ09B0330-0300

20.2.2

System Clock Control Register (SCKCR)

PSTOP

R/W

—

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs

φ clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φφφφ Clock Output Disable (PSTOP): Controls φ output.

Description

Bit 7

PSTOP

Normal

Operating Mode

Sleep Mode

Software

Standby Mode

Hardware

Standby Mode

φ output (initial value)

φ output

Fixed high

High impedance

Fixed high

High impedance

Bits 6—Reserved: This bit can be read or written to, but only 0 should be written.

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus

master.

Bit 2

SCK2

Bit 1

SCK1

Bit 0

SCK0

Description

Bus master in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

—

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