M32CSLASH86T datasheet(213/505 Pages) RENESAS

213 / 505 page

Page 190

17. Serial I/O

)

(

UARTi Special Mode Register 3 (i=0 to 4)

Symbol

Address

After Reset

U0SMR3 to U4SMR3

036516, 02E516, 033516, 032516, 02F516

0016

NODC

ERR

DL0

DL1

SSE

DINC

CKPH

DL2

SS Pin Function

Enable Bit(1)

Clock Phase

Set Bit

Serial Input Port

Set Bit

Clock Output

Select Bit

Fault Error Flag(2)

SDAi Digital Delay

Time Set Bit(3, 4)

0: Disables SS pin function

1: Enables SS pin function

0: No clock delay

1: Clock delay

0: Selects the TxDi and RxDi pins

(master mode)

1: Selects the STxDi and SRxDi pins

(slave mode)

0: CMOS output

1: N-channel open drain output

0: No error

1: Error

000 : No delay

001 : 1-to-2 cycles of BRG count source

010 : 2-to-3 cycles of BRG count source

011 : 3-to-4 cycles of BRG count source

100 : 4-to-5 cycles of BRG count source

101 : 5-to-6 cycles of BRG count source

110 : 6-to-7 cycles of BRG count source

111 : 7-to-8 cycles of BRG count source

b7 b6 b5

Bit Name

Bit

Symbol

Function

NOTES:

1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled).

2. The ERR bit is set to "0" by program. It is unchanged if set to "1".

3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I2C mode. Set these bits to

"0002" (no delay) except in the I2C mode.

4. When the external clock is selected, approximately 100ns delay is added.

Figure 17.7 U0SMR3 to U4SMR3 Registers

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