M16CSLASH62M datasheet(50/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control

1-31

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Table 1.9.4. Operation of RD, WR, and BHE signals

Status of external data bus

BHE

LHL

HLH

Write 1 byte of data to odd address

Read 1 byte of data from odd address

Write 1 byte of data to even address

Read 1 byte of data from even address

Data bus width

LHL

H / L

8-bit

(BYTE = “H”)

Write data to both even and odd addresses

Read data from both even and odd addresses

Write 1 byte of data

Read 1 byte of data

16-bit

(BYTE = “L”)

Not used

Status of external data bus

Read data

Write 1 byte of data to even address

Write 1 byte of data to odd address

Write data to both even and odd addresses

WRH

WRL

Data bus width

16-bit

(BYTE = “L”)

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Table 1.9.3. Operation of RD, WRL, and WRH signals

(3) Read/write signals

With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the

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combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE

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pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0

(address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals.

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After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.

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When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the

processor mode register 0 (address 000416) has been set (Note).

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect

(4) ALE signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the

ALE signal falls.

When BYTE pin = “H”

When BYTE pin = “L”

ALE

Address

Data (Note 1)

Address (Note 2)

D0/A0 to D7/A7

A8 to A19

ALE

Address

Data (Note 1)

Address

D0/A1 to D7/A8

A9 to A19

Address

Note 1: Floating when reading.

Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.

Figure 1.9.3. ALE signal and address/data bus

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