M16CSLASH62M datasheet(78/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt

1-59

Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking

whether interrupt requests are made), the interrupt assigned a higher priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level

select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware

priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are regulated by hardware.

Figure 1.11.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register

(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter

(PC), both of which have been saved in the stack area. Then control returns to the program that was being

executed before the acceptance of the interrupt request, so that the suspended process resumes.

Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-

tion before executing the REIT instruction.

Interrupt resolution circuit

When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest

priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.

Figure 1.11.8. Hardware interrupts priorities

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Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

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