H8SLASH3028F datasheet(333/923 Pages) RENESAS

333 / 923 page

Rev. 2.00, 09/03, page 303 of 890

Pin Functions and Selection Method

The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2

and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit

PB2DDR select the pin function as follows.

DRAM interface

settings

(1) in table below

(2) in

table

below

OIS3/2 and

OS1/0

All 0

Not all 0

—

CS5E

—

PB2DDR

—

NDER10

—

Pin function

PB2

input

PB2

output

TP10

output

CS5

output

TMIO2

output

CS5

output*

Note: *

CS5 is output as RAS5.

DRAM interface

settings

(1)

(2)

(1)

DRAS2

DRAS1

PB2/TP10/

TMO2/CS5

DRAS0

0101

Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in

CSCR, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows.

OIS3/2 and

OS1/0

All 0

Not all 0

CS6E

—

PB1DDR

—

NDER9

—

PB1

input

PB1

output

TP9

output

CS6

output

TMIO1

output

TMIO1 input*

PB1/TP9/

TMIO1/

DREQ0/CS6

Pin function

DREQ0 input*2

Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1.

2. When an external request is specified as a DMAC activation source,

DREQ0 input regardless of bits OIS3/2 and OS1/0, bits CCLR1/0, bit

CS6E, bit NDER9, and bit PB1DDR.

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