H8SLASH3028F datasheet(10/923 Pages) RENESAS

10 / 923 page

Rev. 2.00, 09/03, page x of xxx

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7.4.10 External Bus

Requests, DRAM

Interface, and DMAC

Figure 7.20 Bus

Timing of DRAM

Interface, and DMAC

236

Figure amended

HWR LWR

T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2

DMAC cycle (channel 0)

Refresh

cycle

Address

bus

7.4.14 DMAC States

in Reset State, Standby

Modes, and Sleep

Mode

Figure 7.24 Timing of

Cycle-Steal Transfer in

Sleep Mode

240

Figure amended

Address bus

HWR LWR

CPU cycle

DMAC cycle

Sleep mode

7.6.8 Bus Cycle when

Transfer is Aborted

Figure 7.27 Bus

Timing at Abort of DMA

Transfer in Cycle-Steal

Mode

245

Figure amended

Address bus

HWR, LWR

CPU cycle

DMAC cycle

CPU cycle

DMAC

cycle

CPU cycle

DTE bit is

cleared

12.2.3 Reset Control/

Status Register

(RSTCSR)

Bit 7—Watchdog Timer

Reset (WRST)

442

Description amended

At the same time, if the RSTOE bit is set to 1, the reset signal is

output from the

RESO pin as low-level output to an external

device, making it possible to reset the entire system.

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