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H8/3028F Datasheet(PDF) 435 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 435 Page - Renesas Technology Corp |
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435 / 923 page  Rev. 2.00, 09/03, page 405 of 890 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case. Counter clear signal 8TCNT internal clock 8TCNT N X H'00 T1 T3 T2 Input capture signal φ TCORB N Figure 10.22 Contention between Counter Clearing by Input Capture and Counter Increment |
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