H8SLASH3028F datasheet(492/923 Pages) RENESAS

492 / 923 page

Rev. 2.00, 09/03, page 462 of 890

Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.

Bit 4

Description

Receiving disabled*

(Initial value)

Receiving enabled*

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These

flags retain their previous values.

2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous

mode, or serial clock input is detected in synchronous mode. Select the receive format

in SMR before setting the RE bit to 1.

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in

SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE

Description

Multiprocessor interrupts are disabled (normal receive operation) (Initial value)

[Clearing conditions]

• The MPIE bit is cleared to 0

• MPB = 1 in received data

Multiprocessor interrupts are enabled*

Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of

the RDRF, FER, and ORER status flags in SSR are disabled until data with the

multiprocessor bit set to 1 is received.

Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,

and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which

MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,

enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the

FER and ORER flags to be set.

Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt

(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.

Bit 2

TEIE

Description

Transmit-end interrupt requests (TEI) are disabled*

(Initial value)

Transmit-end interrupt requests (TEI) are enabled*

Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,

then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing

the TEIE bit to 0.

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