H8SLASH3028F datasheet(566/923 Pages) RENESAS

566 / 923 page

Rev. 2.00, 09/03, page 536 of 890

The receive margin can therefore be expressed as follows.

Receive margin in smart card interface mode:

M = (0.5 –

D – 0.5

) – (L – 0.5) F –

(1 + F)

× 100%

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 372)

D: Clock duty cycle (L = 0 to 1.0)

L: Frame length (L =10)

F: Absolute deviation of clock frequency

From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.

When D = 0.5 and F = 0:

M = (0.5 – 1/2

× 372) × 100%

= 49.866%

Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as

described below.

• Retransmission when SCI is in Receive Mode

Figure 14.12 illustrates retransmission when the SCI is in receive mode.

1. If an error is found when the received parity bit is checked, the PER bit is automatically set to

1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit

should be cleared to 0 in SSR before the next parity bit sampling timing.

2. The RDRF bit in SSR is not set for the frame in which the error has occurred.

3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.

4. If no error is found when the received parity bit is checked, the receive operation is assumed to

have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE

bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA

transfer activation source, the RDR contents can be read automatically. When the DMAC

reads the RDR data, the RDRF flag is automatically cleared to 0.

5. When a normal frame is received, the data pin is held in the high-impedance state at the error

signal transmission timing.

H8/3028F Datasheet(PDF) 566 Page - Renesas Technology Corp