H8SLASH3028F datasheet(637/923 Pages) RENESAS

637 / 923 page

Rev. 2.00, 09/03, page 607 of 890

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait (tsswe) µs

Wait (tsesu) µs

n = 1

Set EBR1 or EBR2

Enable WDT

*3 *4

Wait (tse) ms

Wait (tce) µs

Wait (tcesu) µs

Wait (tsev) µs

Set block start address as verify address

Wait (tsevr) µs

Wait (tcev) µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (tcev) µs

Clear EV bit in FLMCR1

Re-erase

Clear SWE bit in FLMCR1

Disable WDT

End of erase

Verify data = all 1s?

Last address of block?

Erase failure

Clear SWE bit in FLMCR1

≥ N?

Yes

← n + 1

Increment

address

Wait (tcswe) µs

Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Verify data is read in 16-bit (word) units.

3. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.

4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.

5. The wait times and the value of N are shown in section 21.2.6, Flash Memory Characteristics.

Perform erasing in block units.

Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)

H8/3028F Datasheet(PDF) 637 Page - Renesas Technology Corp

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